The present disclosure generally relates to wafer level integration for heterogonous wafers, and more particularly relates to methods and structures to support heterogeneous wafer level integration to overcome wafer to wafer stress.
Wafer level integration for heterogonous product function and multi-high function in sub-component and product is challenging due to different structures, materials, coefficients of thermal expansion (CTE), processing, equipment, mechanical stresses and thermal considerations. Non-planarity or warpage and breakage at the wafer level present challenges to manufacturing yields.